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authorAaditya Dhruv <[email protected]>2025-05-03 14:42:04 -0500
committerAaditya Dhruv <[email protected]>2025-05-03 14:42:04 -0500
commit688851c6c56776dc57cb6159840e868f6544d157 (patch)
tree120cc94326e49c9028101ce720c0dec120dc572c
parent27276271a8950811ee6c3f4fc59ded2500ad8b7d (diff)
Add ldh_r16_a() opcode support
-rw-r--r--src/cpu/chip.rs12
1 files changed, 10 insertions, 2 deletions
diff --git a/src/cpu/chip.rs b/src/cpu/chip.rs
index c6a6609..e5af381 100644
--- a/src/cpu/chip.rs
+++ b/src/cpu/chip.rs
@@ -243,8 +243,8 @@ impl Chip {
(0b01, 0b110, 0b110) => { self.halt() }, //HALT
(0b01, dst_r8, src_r8) => { self.ld_r8_r8(src_r8, dst_r8) }, //LD r8, r8
(0b10, op, r8) => { self.alu_a_r8(op, r8); }, //ALU A, r8
- (0b11, 0b000..=0b011, 0b000) => { }, //RET condition
- (0b11, 0b100, 0b000) => { }, //LD (FF00 + u8), A
+ (0b11, 0b000..=0b011, 0b000) => { }, //RET condition
+ (0b11, 0b100, 0b000) => { self.ldh_r16_a(oct2) }, //LD (FF00 + u8), A
(0b11, 0b101, 0b000) => { }, //ADD SP, i8
(0b11, 0b110, 0b000) => { }, //LD A, (FF00 + u8)
(0b11, 0b111, 0b000) => { }, //LD HL, SP + i8
@@ -276,6 +276,14 @@ impl Chip {
}
+ fn ldh_r16_a(&mut self, memory: u8) {
+ let memory: u16 = 0xFF00 + memory as u16;
+ if memory < 0xffff && memory > 0xff00 {
+ let value = self.get_r8_register(7);
+ self.write_memory(memory, value);
+ }
+ }
+
//TODO - Respond to interrupt
fn halt(&mut self) {